1. Field of the Invention
The present invention relates to an imaging device.
Priority is claimed on Japanese Patent Application No. 2012-066152, filed Mar. 22, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, an imaging device represented by a charge coupled device image sensor (hereinafter referred to as the CCD), and a complementary metal oxide semiconductor image sensor (hereinafter referred to as the CMOS) has been installed in an image device represented by a digital still camera, a camcorder, and an endoscope. The imaging devices have gained popularity at home and abroad, and a demand for a further decrease in size and for low power consumption has been high.
Among the CMOS's, the so-called column A/D type imaging device with an A/D conversion function integrated into a column unit has been developed and commercialized. A single slope A/D conversion method, one of the embedded A/D conversion functions, is to compare a reference signal (a ramp wave), which changes monotonously for conversion to a digital signal, with an analog pixel signal, to perform count processing in parallel to the comparison processing, and to obtain the digital signal for a pixel signal based on a count value at the time of completion of the comparison processing.
Particularly, an imaging device is known, which includes a count unit that has multiple delay units, each with the same configuration, generates a low order phase shift CLK using a ring oscillator and the like that starts a transition operation at a timing relating to starting of the comparison processing, and counts pulses from a ring oscillator, a low order latch unit that latches low order logical states, which are logical states of the multiple delay units, at a first timing relating to ending of the comparison processing, and a high order latch unit that latches high order logical states, which are the logical states of the count units, at the first timing relating to the ending of the comparison processing. The imaging device computes a digital signal that depends on an analog signal, based on data obtained by the low order latch unit and the high order latch unit, and perform an A/D conversion (for example, Japanese Unexamined Patent Applications, First Publication No. 2008-92091).
However, in such a case where an A/D conversion circuit is arranged in every multiple pixel (for example, the A/D conversion circuit is arranged in every pixel column), several hundreds to several thousands of A/D conversion circuits have to be arranged at intervals of several μm. Because in this case wiring space is increased, a power source and a GND can not be divided to provide wiring in every A/D conversion circuit. For this reason, the wiring needs to be provided in such a manner that all of the A/D conversion circuits are connected to a common power source and a common GND.
FIG. 5 is a block diagram illustrating an outline of a configuration of the imaging device that has a single slope A/D conversion circuit, known in the related art. In an example illustrated, an imaging device 200 includes an imaging unit 100 of multiple pixels P, the single slope A/D conversion circuit, a reference signal source 101, a horizontal line selection circuit 102, and an output line 109. Furthermore, the single slope A/D conversion circuit includes a ramp wave generator 104, a phase frequency comparator 106, a ring oscillator 107, comparators 103a to 103c, counters 105a to 105c, and latch decode circuits 108a to 108c, each made from a latch circuit and a decode circuit.
Next, operations of the imaging device 200 is described that has the single slope A/D conversion circuit. First, a pixel signal that a pixel P outputs in response to an amount of incident light, and the ramp wave that the ramp wave generator 104 outputs in response to a signal from the reference signal source 101 are input to the comparators 103a to 103c. At the same time, the phase frequency comparator 106 and the ring oscillator 107 generate a count pulse and a pulse that is shifted by π/8 in phase from the count pulse, in response to the signal from the reference signal source 101. The counters 105a to 105c are synchronized with the count pulse from the ring oscillator 107, and starts to count from an initial value thereof. Furthermore, the pulse that is shifted by π/8 in phase from the count value is input to the latch circuit within the latch decoders 108a to 108c. 
When a magnitude relationship between two input signals, which are the pixel signal and the ramp wave that are input to the comparators 103a to 103c in a certain column, is changed, output signals from the comparators 103a to 103c are reversed, the counters 105a to 105c in that column maintain count values, the latch circuits of the latch decoders 108a to 108c in that column maintain states of the pulses, which are shifted by π/8 in phase from the count pulse, with their respective latch units. Subsequently, the pulses, maintained by the latch circuits of the latch decoders 108a to 108c, are supplied to the decode circuits, and are converted into numerical values in several bits (for example, 3 bits) according to the states of the maintained pulses. Thus, the pixel signal, output by the pixel P, may be A/D-converted.
FIG. 6 is a block diagram illustrating an outline of a configuration of an A/D conversion unit that is equipped with the single slope A/D conversion circuit that is known in the related art. As illustrated in FIG. 6, the counters 105a to 105j included in the A/D conversion circuit arranged in each column of the A/D conversion unit 300 have the same configurations as the latch decoders 108a to 108j. Furthermore, the operating electric current for the latch units of the latch circuits included in the latch decoder 108a to 108j flows when the pulse that is input is changed (for example, when the pulse is changed from high to low, or from low to high). For this reason, in a case where the same pulse is input to the multiple latch units, the electric current flows in the power source and the GND, which are commonly wired to the latch units to which the same pulse is input, at almost the same timing. Because of the electric current, a voltage drop occurs in resistance components of the input wiring and the GND wiring, and voltage levels of the power source and the GND of each latch unit are changed.
The imaging device that is used in a digital still camera (DSC) is considered as an example. Normally, the number of pixels of the digital still camera is one million or more. Here, the number of pixels of the digital still camera is assumed to be 20 million. For the purpose of conveniences for the descriptions, an aspect ratio in a 20 million pixel array is assumed to be 4000 rows×5000 columns. In a case where a readout of 60 frames per one second (60 frames/sec) is realized, a phase shift pulse and a counter pulse are approximately several hundred MHz. At this time, an amount of operating electric current for at least significant bit (LSB) of the latch unit and the counter ranges from 10 μA to 20 μA. In a case where one A/D conversion circuit is provided per one column, the amount of electric current flowing in all of the latch units that are horizontally in parallel is (10 μA to 20 μA)×5000 columns=50 mA to 100 mA.
It is likely that when a wiring resistance of the power source is set to 5 Ω, a fluctuation will be 0.5 V, and when a power source voltage is set to approximately 1.5 V, a power source potential and GND potential will be changed by approximately 30 to 40 percents and malfunction will occur in the latch decoders 108a to 108j and the counters 105a to 105j. Particularly, a fluctuation in the power source has a great influence on the counters 105a to 105j and the latch decoders 108a to 108j that are arranged in a column far away from a power supply that supplies the power source and the GND.
In this manner, in a case where the multiple A/D conversion circuits are connected to the common power source and the common GND, the voltage drop occurs in the resistance components of the input wiring and the GND wiring, and the voltage levels of the power source and the GND of each A/D conversion circuit are changed.